1. Field of the Invention
The invention relates to digital frequency synthesizers and/or particularly to digital frequency synthesizers employing residue number system based processors.
2. Background Art
It is well known that analog signals of a number of different frequencies may be generated from a single source frequency by the use of analog circuits or by a combination of analog and digital circuits. In a technique known as Direct Digital Frequency Synthesis, digital data representing samples of sinusoidal wave forms of different frequencies are converted to analog sinusoidal output signals using a digital-to-analog converter. In many cases the digital data is acquired from a memory, in which are stored the values of a single cycle (or portion thereof) of a sinusoidal wave form taken at uniformly spaced intervals. The sequence of digital data points to be converted is generated by retrieval of the stored points in a uniform fashion, usually periodic. The methodology for generating the data points is well known and described in technical publications. The circuitry for selecting and retrieving the appropriate digital samples to be applied to the digital-to-analog converter is generally referred to as a numerically controlled oscillator and may be used independently of the converter. State-of-the-art numerically controlled oscillators are typically implemented in integrated circuitry.
As a result of ever more stringent performance specifications required of frequency synthesizers for many different applications, such as spread spectrum and frequency hopping and other high precision applications, interest in direct digital synthesizers has increased. For high precision applications, the direct digital frequency synthesizers offer important advantages over analog synthesizers. They offer ultrahigh frequency resolutions, exceptionally fast and phasecontinuous frequency switching and the reproducibility inherent in the use of digital techniques.
Most direct digital frequency synthesizers use essentially the same method, referred to as the Sine Table Lookup Method. In this method, a sinusoidal output signal is generated by periodically accessing stored digital samples of a sine wave and converting the samples to an analog signal by means of a digital-to-analog converter. The memory in which the samples are stored is commonly addressed from a sequential address generator. The basic structure of a typical prior art direct digital frequency synthesizer is shown in FIG. 1. The direct digital frequency synthesizer consists of a numerically controlled oscillator 100 driving a translator 103, read-only memory 105, latch 106, digital-to-analog converter (DAC) 107, and low pass filter (LPF) 108. The numerically controlled oscillator, 100, also known as an address generator or phase accumulator, consists of a binary adder 101 and latch 102 in which the adder output is latched in every clock cycle of the system clock f.sub.c. A digital frequency setting word k defining an address increment value is applied to the adder 101. The output of the latch 102, which stores the output of the adder 101, is added to the frequency setting word in each clock cycle using feedback. Thus, a new memory address is generated in each clock cycle. Furthermore, successive memory addresses differ by the value of the frequency setting word. The output of the latch 102 is applied to a translator 103 before it is applied to a read-only memory (ROM) 105. The read-only memory 105 typically stores data words representing samples taken at uniformly spaced intervals on a single period (or portion thereof) of a sine wave form. The frequency setting word defines the spacing between the accessed memory samples, and in so doing determines the frequency of the output wave form. Since sinusoidal wave forms possess quarter-wave symmetry, the memory 105 typically stores the values for only one quadrant of the sine wave, and the translator 103 modifies the phase accumulator-computed address accordingly so that the proper sample value is accessed. The output from the memory 105 is clocked to a latch 106 and applied to a digital-to-analog converter 107 to generate the corresponding analog sine wave. The generated sine wave usually is passed through a low pass filter 108 to smooth out the generated signal.
There are several figures of merit for direct digital frequency synthesizers. They include frequency resolution, frequency range and frequency switching time. Frequency resolution is the smallest change that can be generated in the output frequency. Alternatively, it is the lowest non-zero frequency that can be generated. It is improved (i.e., made smaller) by increasing the width (i.e., the number of bits) in the phase accumulator adder. Frequency range is the largest frequency that can he generated. It is dependent on the system clock frequency f.sub.c (see FIG. 1). Frequency switching time is the time required to change the frequency of the output signal from one frequency to another. This represents the time for the new value of k and its effects to pass through all the circuitry from the Phase Accumulator to the output.
In a typical binary adder, as used in the Phase Accumulator 100, the time required to perform addition increases as a function of the number of bits in the operands that are being added, since their corresponding bits must be added on a bit by bit basis, taking into consideration a carry-out output from the neighboring less significant bit. It is not uncommon for direct digital frequency synthesizers to use a 36 or 40 bit wide frequency setting word and adder. Thus, the addition process in the Phase Accumulator is relatively slow, and is considered to be the "bottleneck" in these devices. To reduce the effects of this time delay on the data throughput rate, pipelined binary adders are frequently used. Pipelined binary adders add the two operands together bit-by-bit, one pair of bits per clock cycle. In this "assembly line" fashion, many partial sums are being computed at any time, and an adder output sum is generated in each clock cycle. FIG. 2 is a diagrammatic representation of a typical pipelined binary adder architecture, widely used in the art. The binary adder of FIG. 2 is a 4-bit binary adder pipelined into four separate stages. A.sub.0, B.sub.0 through A.sub.3, B.sub.3 shown in FIG. 2 represent operands to be added. C.sub.in represents an input carry and C.sub.0 through C.sub.2 represent intermediate carry outputs. C.sub.0 and S.sub.0 through S.sub.3 represent the output of the adder. Individual stages are separated by latches that are clocked by the system clock signal f.sub.c. The 4-bit, 4-stage adder requires four clock cycles before the sum is properly generated. However, once the pipeline is filled, a new adder output sum is generated in every clock cycle. This represents an increase in data throughput rate above that which would be achieved without pipelining.
A problem arises when a change of input operand must be made. In the phase accumulator, this corresponds to a switch of the frequency setting word k. That is, to switch over from one analog output frequency to another, the frequency setting word is changed. However, all internally latched data in the pipeline adder must be cleared before the new output is generated, introducing a significant delay. By way of example, in a 36 bit-pipelined adder, there are 36 pipelined stages, and the frequency switching time therefore is 36 clock cycles. This time period is referred to as latency. It will be readily apparent that a low latency accumulator is desirable. For example, in frequency modulation applications, the speed with which the output frequency can be changed determines the maximum frequency of the information signal that can be used to modulate a carrier. The lower the latency, therefore, the higher the maximum frequency of the signal. One attempt at providing a low latency accumulator is described in a technical paper entitled "Low-Latency, High-Speed Numerically Controlled Oscillator Using Progression-Of-States Technique," by Matthew Thompson, IEEE Journal of Solid-State Circuits, Volume 27, No. 1, January, 1992, pp. 113-117. The Thompson paper proposes to reduce latency in a numerically controlled oscillator by essentially replacing pipeline stages by output feedback, essentially "folding" the stages into one another. This scheme necessitates holding the frequency setting word constant for four clock cycles. Such a solution is impractical because, despite the fact that it reduces the number of pipeline stages, it does not solve the essence of the latency problem, which is the speed with which the output sinusoid frequency can be changed.
As stated earlier, high frequency resolution implies a large number of bits used to represent the frequency setting word and, therefore, a large adder, consuming a sizable amount of chip area in an integrated circuit implementation. This large adder will contain many pipeline stages and will possess a large latency. Also, in integrated circuit implementations the memory which stores the samples to be applied to the digital-to-analog converter, typically a read-only-memory (ROM), consumes much of the chip area. It is well known that larger chip areas mean lower manufacturing yields and higher costs. For this reason, it is desirable to reduce the size of the ROM, without, of course, reducing the capabilities of the circuit.